Recent rates of improvement in transistor scaling have been much lower than previous decades. Hence hardware customization for more efficient use of the transistors on a VLSI chip is now a primary means for performance improvement. These trends towards increased hardware customization present challenges that should  be addressed by compilers: i) How can performance-portable and productive application development for diverse hardware platforms be achieved? ii) How can architectural parameters for hardware accelerators be optimized for execution of key workloads?

The state-of-the-art in optimizing compilers is very advanced with respect to lowering programs from high-level languages to low-level instruction sets so as to minimize the number of executed instructions.  However, the fundamental bottleneck today is not the number of executed arithmetic/logic instructions but the cost of data access and movement, both in terms of energy as well as time.  Many program transformation techniques such as loop tiling/fusion and data layout transformation have been devised to address this critical bottleneck. But while these techniques have been used in creating manually optimized libraries, effective automated data-locality optimization by compilers remains a challenge. For some classes of matrix/tensor computations used in high-impact domains like machine learning, progress has been made in defining and exploring search spaces for automated code optimization for multiple hardware targets. This talk will elaborate on a number of key challenges/opportunities for compilers, including design space exploration, effective performance modeling, algorithm-architecture co-design and derivation of lower bounds on data movement.